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1 8393bs-mcu wireless-02/13 atmega256/128/64rfr2 8-bit microcontroller with low power 2.4ghz transceiver for zigbee and ieee 802.15.4 atmega256rfr2 atmega128rfr2 atmega64rfr2 8393bs-mcu wireless-02/13 features ? network support by hardware assisted multiple pan a ddress filtering ? advanced hardware assisted reduced power consumptio n ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture - 135 powerful instructions ? most single clock cycle execution - 32x8 general purpose working registers / on-chip 2- cycle multiplier - up to 16 mips throughput at 16 mhz and 1.8v ? fully static operation ? non-volatile program and data memories - 256k/128k/64k bytes of in-system self-programmable flash ? endurance: 10?000 write/erase cycles @ 125c (25?00 0 cycles @ 85c) - 8k/4k/2k bytes eeprom ? endurance: 20?000 write/erase cycles @ 125c (100?0 00 cycles @ 25c) - 32k/16k/8k bytes internal sram ? jtag (ieee std. 1149.1 compliant) interface - boundary-scan capabilities according to the jtag st andard - extensive on-chip debug support - programming of flash eeprom, fuses and lock bits th rough the jtag interface ? peripheral features - multiple timer/counter & pwm channels - real time counter with separate oscillator - 10-bit, 330 ks/s a/d converter; analog comparator; on-chip temperature sensor - master/slave spi serial interface - two programmable serial usart - byte oriented 2-wire serial interface ? advanced interrupt handler and power save modes ? watchdog timer with separate on-chip oscillator ? power-on reset and low current brown-out detector ? fully integrated low power transceiver for 2.4 ghz ism band - high power amplifier support by tx spectrum side lo be suppression - supported data rates: 250 kb/s and 500 kb/s, 1 mb/s , 2 mb/s - -100 dbm rx sensitivity; tx output power up to 3.5 dbm - hardware assisted mac (auto-acknowledge, auto-retry ) - 32 bit ieee 802.15.4 symbol counter - sfd-detection, spreading; de-spreading; framing ; c rc-16 computation - antenna diversity and tx/rx control / tx/rx 128 byt e frame buffer - phase measurement support ? pll synthesizer with 5 mhz and 500 khz channel spac ing for 2.4 ghz ism band ? hardware security (aes, true random generator) ? integrated crystal oscillators (32.768 khz & 16 mhz , external crystal needed) ? i/o and package - 38 programmable i/o lines - 64-pad qfn (rohs/fully green) ? temperature range: -40c to 125c industrial ? ultra low power consumption (1.8 to 3.6v) for avr & rx/tx: 10.1ma/18.6 ma - cpu active mode (16mhz): 4.1 ma - 2.4ghz transceiver: rx_on 6.0 ma / tx 14.5 ma (maxi mum tx output power) - deep sleep mode: <700na @ 25c ? speed grade: 0 ? 16 mhz @ 1.8 ? 3.6v range with int egrated voltage regulators applications ? zigbee ? / ieee 802.15.4-2011/2006/2003 ? ? full and reduced function device ? general purpose 2.4ghz ism band transceiver with mi crocontroller ? rf4ce, sp100, wirelesshart ? , ism applications and ipv6 / 6lowpan
2 8393bs-mcu wireless-02/13 atmega256/128/64rfr2 1 pin configurations figure 1-1. pinout atmega256/128/64rfr2 note: the large center pad underneath the qfn/mlf package is made of metal and internally connected to avss. it should be soldered or glued to the boar d to ensure good mechanical stability. if the center pad is left unco nnected, the package might loosen from the board. i t is not recommended to use the exposed paddle as a replacement of the regu lar avss pins. 2 disclaimer typical values contained in this datasheet are base d on simulation and characterization results of other avr microcontrollers and radio tra nsceivers manufactured in a similar process technology. minimum and maximum values will be available after the device is characterized. 1 [pf3:adc3:dig4] [pf2:adc2:dig2] 2 3 [pf5:adc5:tms] [pf4:adc4:tck] 4 5 [pf7:adc7:tdi] [pf6:adc6:tdo] 6 7 [rfp] [avss_rfp] 8 9 [avss_rfn] [rfn] 10 11 [rstn] [tst] 12 13 14 [rston] [pg0:dig3] 56 55 54 53 52 51 62 61 60 59 58 57 64 63 atmega256/128/64rfr2 exposed paddle: [avss] [dvss] [pe0:rxd0:pcint8] [pe1:txd0] [pe2:xck0:ain0] [clki] [devdd] [dvss] [pb0:ssn:pcint0] [pb1:sck:pcint1] [pb2:mosi:pdi:pcint2] [pb3:miso:pdo:pcint3] [pb4:oc2a:pcint4] [pb5:oc1a:pcint5] [pb6:oc1b:pcint6] 31 32 17 18 19 20 21 23 22 24 25 26 27 0 28 [pd3:txd1:int3] [pd2:rxd1:int2] [pd1:sda:int1] [pd0:scl:int0] [dvss] [devdd] [dvdd] [dvdd] [dvss:dsvss] [pg5:oc0b] [pg4:tosc1] [pg3:tosc2] [pd7:t0] [pd6:t1] 42 41 40 39 38 37 36 35 34 33 48 47 46 45 15 16 [pg1:dig1] [pg2:amr] [pb7:oc0a:oc1c:pcint7] [devdd] 44 43 29 0 30 [pd5:xck1] [pd4:icp1] 50 49 index corner [devdd] [pe7:icp3:int7:clko] [pe6:t3:int6] [pe5:o c3c:int5] [pe4:oc3b:int4] [pe3:oc3a:ain1] [xtal2] [dvss] [pf1:adc1] [pf0:adc0] [aref] [avss] [avdd] [evdd] [avss:asvss] [xtal1]
3 8393bs-mcu wireless-02/13 atmega256/128/64rfr2 3 overview the atmega256/128/64rfr2 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture combined with a high data rate transceiver for the 2.4 ghz ism band. by executing powerful instructions in a single cloc k cycle, the device achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. the radio transceiver provides high data rates from 250 kb/s up to 2 mb/s, frame handling, outstanding receiver sensitivity and high transmit output power enabling a very robust wireless communication. 3.1 block diagram figure 3-1 block diagram the avr core combines a rich instruction set with 3 2 general purpose working registers. all 32 registers are directly connected to the arithmetic logic unit (alu). two independent registers can be accessed with one sing le instruction executed in one clock cycle. the resulting architecture is very cod e efficient while achieving throughputs up to ten times faster than conventional cisc micro controllers. the system includes internal voltage regulation and an advanced power m anagement. distinguished by the small leakage current it allows an extended operati on time from battery. the radio transceiver is a fully integrated zigbee solution using a minimum number of external components. it combines excellent rf perfo rmance with low cost, small size and low current consumption. the radio transceiver includes a crystal stabilized fractional-n synthesizer, transmitter and receiver, and full direct sequence spread
4 8393bs-mcu wireless-02/13 atmega256/128/64rfr2 spectrum signal (dsss) processing with spreading an d despreading. the device is fully compatible with ieee802.15.4-2011/2006/2003 a nd zigbee standards. the atmega256/128/64rfr2 provides the following fea tures: 256k/128k/64k bytes of in-system programmable (isp) flash with read-while- write capabilities, 8k/4k/2k bytes eeprom, 32k/16k/8k bytes sram, up to 35 general pur pose i/o lines, 32 general purpose working registers, real time counter (rtc), 6 flexible timer/counters with compare modes and pwm, a 32 bit timer/counter, 2 us art, a byte oriented 2-wire serial interface, a 8 channel, 10 bit analog to dig ital converter (adc) with an optional differential input stage with programmable gain, pr ogrammable watchdog timer with internal oscillator, a spi serial port, ieee std. 1 149.1 compliant jtag test interface, also used for accessing the on-chip debug system an d programming and 6 software selectable power saving modes. the idle mode stops the cpu while allowing the sram , timer/counters, spi port, and interrupt system to continue functioning. the power -down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. in power-save mode, th e asynchronous timer continues to run, allowing the user to maintain a timer base whi le the rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o modules except asynchronous timer and adc, to minimize switching n oise during adc conversions. in standby mode, the rc oscillator is running while th e rest of the device is sleeping. this allows very fast start-up combined with low power c onsumption. in extended standby mode, both the main rc oscillator and the asynchron ous timer continue to run. typical supply current of the microcontroller with cpu clock set to 16mhz and the radio transceiver for the most important states is shown in the figure 3-2 below . figure 3-2 radio transceiver and microcontroller (16mhz) supp ly current 16,6ma 4,7ma 4,1ma 250na 18,6ma 0 5 10 15 20 deep sleep sleep trx_off rx_on busy_tx radio transceiver and microcontroller (16mhz) suppl y current i(devdd,evdd) [ma] 1.8v 3.0v 3.6v the transmit output power is set to maximum. if the radio transceiver is in sleep mode the current is dissipated by the avr microcontrolle r only. in deep sleep mode all major digital blocks with no data retention requirements are disconnected from main supply providing a very smal l leakage current. watchdog timer, mac symbol counter and 32.768khz oscillator can be configured to continue to run. 700 na rpc enabled 10.1ma rpc disabled
5 8393bs-mcu wireless-02/13 atmega256/128/64rfr2 the device is manufactured using atmel?s high-densi ty nonvolatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system trough an spi serial interface, by a conventional n onvolatile memory programmer, or by on on-chip boot program running on the avr core. th e boot program can use any interface to download the application program in th e application flash memory. software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. by combining an 8 bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel atmega256/128/64rfr2 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded contro l applications. the atmega256/128/64rfr2 avr is supported with a fu ll suite of program and system development tools including: c compiler, macro asse mblers, program debugger/simulators, in-circuit emulators, and eval uation kits. 3.2 pin descriptions 3.2.1 evdd external analog supply voltage. 3.2.2 devdd external digital supply voltage. 3.2.3 avdd regulated analog supply voltage (internally generat ed). 3.2.4 dvdd regulated digital supply voltage (internally genera ted). 3.2.5 dvss digital ground. 3.2.6 avss analog ground. 3.2.7 port b (pb7...pb0) port b is an 8-bit bi-directional i/o port with int ernal pull-up resistors (selected for each bit). the port b output buffers have symmetrical dr ive characteristics with both high sink and source capability. as inputs, port b pins that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also provides functions of various special f eatures of the atmega256/128/64rfr2. 3.2.8 port d (pd7...pd0) port d is an 8-bit bi-directional i/o port with int ernal pull-up resistors (selected for each bit). the port d output buffers have symmetrical dr ive characteristics with both high sink and source capability. as inputs, port d pins that are externally pulled low will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also provides functions of various special f eatures of the atmega256/128/64rfr2. 3.2.9 port e (pe7...pe0) port e is an 8-bit bi-directional i/o port with int ernal pull-up resistors (selected for each bit). the port e output buffers have symmetrical dr ive characteristics with both high sink and source capability. as inputs, port e pins that are externally pulled low will source
6 8393bs-mcu wireless-02/13 atmega256/128/64rfr2 current if the pull-up resistors are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. port e also provides functions of various special f eatures of the atmega256/128/64rfr2. 3.2.10 port f (pf7...pf0) port f is an 8-bit bi-directional i/o port with int ernal pull-up resistors (selected for each bit). the port f output buffers have symmetrical dr ive characteristics with both high sink and source capability. as inputs, port f pins that are externally pulled low will source current if the pull-up resistors are activated. the port f pins are tri-stated when a reset condition becomes active, even if the clock is not running. port f also provides functions of various special f eatures of the atmega256/128/64rfr2. 3.2.11 port g (pg5?pg0) port g is a 6-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port g output buffers have symmetrical dr ive characteristics with both high sink and source capability. however the driver stre ngth of pg3 and pg4 is reduced compared to the other port pins. the output voltage drop (v oh , v ol ) is higher while the leakage current is smaller. as inputs, port g pins that are externally pulled low will source current if the pull-up resistors are activat ed. the port g pins are tri-stated when a reset condition becomes active, even if the clock is not running. port g also provides functions of various special f eatures of the atmega256/128/64rfr2. 3.2.12 avss_rfp avss_rfp is a dedicated ground pin for the bi-direc tional, differential rf i/o port. 3.2.13 avss_rfn avss_rfn is a dedicated ground pin for the bi-direc tional, differential rf i/o port. 3.2.14 rfp rfp is the positive terminal for the bi-directional , differential rf i/o port. 3.2.15 rfn rfn is the negative terminal for the bi-directional , differential rf i/o port. 3.2.16 rstn reset input. a low level on this pin for longer tha n the minimum pulse length will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. 3.2.17 rston reset output. a low level on this pin indicates a r eset initiated by the internal reset sources or the pin rstn. 3.2.18 xtal1 input to the inverting 16mhz crystal oscillator amp lifier. in general a crystal between xtal1 and xtal2 provides the 16mhz reference clock of the radio transceiver. 3.2.19 xtal2 output of the inverting 16mhz crystal oscillator am plifier. 3.2.20 aref reference voltage output of the a/d converter. in g eneral this pin is left open. 3.2.21 tst programming and test mode enable pin. if pin tst is not used pull it to low.
7 8393bs-mcu wireless-02/13 atmega256/128/64rfr2 3.2.22 clki input to the clock system. if selected, it provides the operating clock of the microcontroller. 3.3 unused pins floating pins can cause power dissipation in the di gital input stage. they should be connected to an appropriate source. in normal opera tion modes the internal pull-up resistors can be enabled (in reset all gpio are con figured as input and the pull-up resistors are still not enabled). bi-directional i/o pins shall not be connected to g round or power supply directly. the digital input pins tst and clki must be connect ed. if unused pin tst can be connected to avss while clki should be connected to dvss. output pins are driven by the device and do not flo at. power supply pins respective ground supply pins are connected together internall y. xtal1 and xtal2 shall never be forced to supply vol tage at the same time. 3.4 configuration summary according to the application requirements a variabl e memory size allows to optimize current consumption and leakage current. table 3-1 memory configuration device flash eeprom sram atmega256rfr2 256kb 8kb 32kb atmega128rfr2 128kb 4kb 16kb atmega64rfr2 64kb 2kb 8kb package and associated pin configuration are the sa me for all devices providing full functionality to the application. table 3-2 system configuration device package gpio serial if adc channel atmega256rfr2 qfn 38 2 usart, spi, twi 8 atmega128rfr2 qfn 38 2 usart, spi, twi 8 atmega64rfr2 qfn 38 2 usart, spi, twi 8 the devices are optimized for applications based on the zigbee and the ieee 802.15.4 specification. having application stack, network la yer, sensor interface and an excellent power control combined in a single chip many years of operation should be possible. table 3-3 application profile device application atmega256rfr2 large network coordinator / router fo r ieee 802.15.4 / zigbee pro atmega128rfr2 network coordinator / router for ieee 802.15.4 atmega64rfr2 end node device / network processor
8 8393bs-mcu wireless-02/13 atmega256/128/64rfr2 3.5 compatibility to atmega1281/2561 the basic avr feature set of the atmega256/128/64rf r2 is derived from the atmega1281/2561. address locations and names of the implemented modules and registers are unchanged as long as it fits the targ et application of a very small and power efficient radio system. in addition, several new features were added. backward compatibility of the atmega256/128/64rfr2 to the atmega1281/2561 is provided in most cases. however some incompatibilit ies between the microcontrollers exist. 3.5.1 port a and port c port a and port c are not implemented. the associat ed registers are available but will not provide any port control. remaining ports are k ept at their original address location to not require changes of existing software package s. 3.5.2 external memory interface the alternate pin function ?external memory interfa ce? using port a and port c is not implemented due to the missing ports. the large internal data memory (sram) does not requ ire an external memory and the associated parallel interface. it keeps the system radiation (emc) at a very small level to provide very high sensitivity at the antenna inp ut. 3.5.3 high voltage programming mode alternate pin function bs2 (high voltage programmin g) of pin pa0 is mapped to a different pin. entering the parallel programming mo de is controlled by the tst pin. 3.5.4 avr oscillators and external clock the avr microcontroller can utilize the high perfor mance crystal oscillator of the 2.4ghz transceiver connected to the pins xtal1 and xtal2. an external clock can be applied to the microcontroller using the clock inpu t clki. 3.5.5 analog frontend the atmega256/128/64rfr2 has a new a/d converter. s oftware compatibility is basically assured. nevertheless to benefit from the higher conversion speeds and the better performance some changes are required.
9 8393bs-mcu wireless-02/13 atmega256/128/64rfr2 4 application circuits 4.1 basic application schematic a basic application schematic of the atmega256/128/ 64rfr2 with a single-ended rf connector is shown in figure 4-1 below and the associated bill of material in table 4-1 on page 10 . the 50 single-ended rf input is transformed to the 100 differential rf port impedance using balun b1. the capacitors c1 an d c2 provide ac coupling of the rf input to the rf port, capacitor c4 improves matc hing. figure 4-1. basic application schematic (64-pin package) 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 5657585960616263 aref avss avss rfp rfn avss tst dvss dvdd dvdd xtal2 devdd dvss avdd evdd avss xtal1 41 42 43 44 45 46 47 48 pb0 dvss pe0 pb7 cb3 cb4 rstn v dd xtal cx1 cx2 cb1 v dd cb2 c1 c2 b1 rf c4 25 26 27 28 29 30 31 32 16 14 13 12 11 10 9 15 64 5455 495051 5253 33 34 35 36 37 38 39 40 rston xtal 32khz cx3 cx4 clki devdd dvss devdd pe7 dvss devdd pf0 pf7 pg0 pg5 pd0 pd7 pins tst & clki must be connected the power supply bypass capacitors (cb2, cb4) are c onnected to the external analog supply pin (evdd, pin 59) and external digital supp ly pin (devdd, pin 23). pins 34, 44 and 54 supply the digital port pins. floating pins can cause excessive power dissipation (e.g. during power on). they should be connected to an appropriate source. gpio shall not be connected to ground or power supply directly. the digital input pins tst and clki must be connect ed. if pin tst will never be used it can be connected to avss while an unused pin clki c ould be connected to dvss (see chapter "unused pins" on page 7 ). capacitors cb1 and cb3 are bypass capacitors for th e integrated analog and digital voltage regulators to ensure stable operation and t o improve noise immunity.
10 8393bs-mcu wireless-02/13 atmega256/128/64rfr2 capacitors should be placed as close as possible to the pins and should have a low- resistance and low-inductance connection to ground to achieve the best performance. the crystal (xtal), the two load capacitors (cx1, c x2), and the internal circuitry connected to pins xtal1 and xtal2 form the 16mhz cr ystal oscillator for the 2.4ghz transceiver. to achieve the best accuracy and stabi lity of the reference frequency, large parasitic capacitances must be avoided. crystal lin es should be routed as short as possible and not in proximity of digital i/o signal s. this is especially required for the high data rate modes. the 32.768 khz crystal connected to the internal lo w power (sub 1 a) crystal oscillator provides a stable time reference for all low power modes including 32 bit ieee 802.15.4 symbol counter ( "mac symbol counter" ) and real time clock application using the asynchronous timer t/c2 ( "timer/counter2 with pwm and asynchronous operation " ). total shunt capacitance including cx3, cx4 should n ot exceed 15pf across both pins. the very low supply current of the oscillator requi res careful layout of the pcb and any leakage path must be avoided. crosstalk and radiation from switching digital sign als to the crystal pins or the rf pins can degrade the system performance. the programming of minimum drive strength settings for the digital output signal is recommend ed (see "dpds0 - port driver strength register 0" ). table 4-1. bill of materials (bom) designator description value manufacturer part numb er comment b1 smd balun smd balun / filter 2.4 ghz wuerth johanson technology 748421245 2450fb15l0001 filter included cb1 cb3 ldo vreg bypass capacitor 1 f (100nf minimum) avx murata 0603yd105kat2a grm188r61c105ka12d x5r (0603) 10% 16v cb2 cb4 power supply bypass capacitor 1 f (100nf minimum) cx1, cx2 16mhz crystal load capacitor 12 pf avx murata 06035a120ja grp1886c1h120ja01 cog (0603) 5% 50v cx3, cx4 32.768khz crystal load capacitor 12 ? 25 pf c1, c2 rf coupling capacitor 22 pf epcos epcos avx b37930 b37920 06035a220jat2a c0g 5% 50v (0402 or 0603) c4 (optional) rf matching 0.47 pf johnstech xtal crystal cx-4025 16 mhz sx-4025 16 mhz acal taitjen siward xwbbpl-f-1 a207-011 xtal 32khz crystal rs=100 kohm 4.2 extended feature set application schematic the atmega256/128/64rfr2 supports additional featur es like: ? security module (aes) ? high data rate mode up to 2mbits/s ? antenna diversity using alternate pin function dig 1/2 at port g and f
11 8393bs-mcu wireless-02/13 atmega256/128/64rfr2 ? rx/tx indicator using alternate pin function dig3/ 4 at port g and f an extended feature set application schematic illus trating the use of the atmega256/128/64rfr2 extended feature set, is shown in figure 4-2 below . figure 4-2. extended feature application schematic 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 56 57 58 59 60 61 62 63 aref avss avss rfp rfn avss tst dvss dvdd dvdd xtal2 devdd dvss avdd evdd avss xtal1 41 42 43 44 45 46 47 48 pb0 dvss pe0 pb7 cb3 cb4 rstn v dd xtal cx1 cx2 cb1 v dd cb2 25 26 27 28 29 30 31 32 16 14 13 12 11 10 9 15 64 54 55 49 50 51 52 53 33 34 35 36 37 38 39 40 rston xtal 32khz cx3 cx4 clki devdd dvss devdd pe7 dvss devdd pf0 pf7 pg0 pg5 pd0 pd7 balun rf- switch ant0 ant1 rf- switch b1 sw1 sw2 pa lna n1 n2 pins tst & clki must be connected although this example shows all additional hardware features combined, it is possible to use all features separately or in various combinati ons.
12 8393bs-mcu wireless-02/13 atmega256/128/64rfr2 5 revision history please note that the referring page numbers in this section are referring to this document. the referring revision in this section ar e referring to the document revision rev. 8393bs-mcu wireless-02/13 1. phase measurement support added to page 1. rev. 8393as-mcu wireless-11/12 1. initial release
13 8393bs-mcu wireless-02/13 atmega256/128/64rfr2 table of contents features .......................................... ................................................... ..... 1 applications ...................................... ................................................... .. 1 1 pin configurations .............................. ................................................ 2 2 disclaimer ...................................... ................................................... ... 2 3 overview ........................................ ................................................... ... 3 3.1 block diagram ................................. ................................................... .................... 3 3.2 pin descriptions............................... ................................................... .................... 5 3.3 unused pins ................................... ................................................... ..................... 7 3.4 configuration summary ......................... ................................................... .............. 7 3.5 compatibility to atmega1281/2561 .............. ................................................... ...... 8 4 application circuits ............................ ................................................ 9 4.1 basic application schematic ................... ................................................... ............ 9 4.2 extended feature set application schematic .... .................................................. 10 5 revision history ................................ ................................................ 12 table of contents ................................. ................................................ 13
14 8393bs-mcu wireless-02/13 atmega256/128/64rfr2 atmel corporation 1600 technology drive san jose, ca 95110 usa tel: (+1)(408) 441-0311 fax: (+1)(408) 487-2600 www.atmel.com atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan g.k. 16f shin-osaki kangyo bldg. 1-6-4 osaki, shinagawa-ku tokyo 141-0032 japan tel: (+81)(3) 6417-0300 fax: (+81)(3) 6417-0370 ? 2013 atmel corporation. all rights reserved. / rev.: 8393bs-mcu wireless-02/13 atmel ? , atmel logo and combinations thereof, enabling unl imited possibilities ? , and others are registered trademarks or trademark s of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provid ed in connection with atmel products. no license, expre ss or implied, by estoppel or otherwise, to any intellec tual property right is granted by this document or in connection with the sale of atmel prod ucts. except as set forth in the atmel terms and cond itions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its produ cts including, but not limited to, the implied warranty of merchantability, fitness for a particul ar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental dama ges (including, without limitation, damages for los s and profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and rese rves the right to make changes to specifications and produc ts descriptions at any time without notice. atmel does not make any commitment to up date the information contained herein. unless specifical ly provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel products are not intende d, authorized, or warranted for use as components in app lications intended to support or sustain life.

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